1. Field
The present disclosure relates generally to central processing units and more particularly to transport triggered architecture central processing units. Still more particularly, the present disclosure relates to a system and method for utilizing microcode to create operations for transport triggered architecture central processing units.
2. Background
In a traditional central processing unit (CPU), high level instructions are decoded and execute microcoded instructions to perform operations. This is typical of both Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC). These microcode programs orchestrate the transfer of data from one CPU resource to another CPU resource in sequence. However, traditional RISC and CISC CPUs are difficult to modify or augment and are not well-suited for reconfigurable computing because it is difficult to modify the architecture of the CPU arbitrarily. Where simplified modification or reconfiguration is desired, a transport triggered architecture is one possible solution. The transport triggered architecture instruction set is virtually like microcode being exposed to the programmer level. However, this means that some complex operations will require multiple instructions.
Some CPUs with transport triggered architecture will rely on a compiler to expand pseudo operations into complex sequences or call subroutines. On a transport triggered architecture processor, calling a subroutine is often a multiple cycle operation in and of itself. Another option is to have the compiler expand a single macro instruction to a sequence of instructions, which requires large amounts of program space usage.
Therefore, it would be advantageous to have a method and apparatus that addresses one or more of the issues discussed above.